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AMD Athlon MP 2100+
General Info
Designer	AMD
Manufacturer	AMD
Model Number	Athlon MP 2100+
Part Number	AMP2100DMS3C
Market	Server
Introduction	June 19, 2002 (announced) June 19, 2002 (launched)
Release Price	$262
Shop	Amazon
General Specs
Family	Athlon MP
Locked	Yes
Frequency	1,733 MHz
Bus type	FSB
Bus speed	133 MHz
Bus rate	266 MT/s
Clock multiplier	13
CPUID	662
Microarchitecture
Microarchitecture	K7
Platform	Athlon MP
Chipset	AMD-760MP
Core Name	Palomino
Core Family	6
Core Model	6
Core Stepping	2
Process	180 nm
Transistors	37,500,000
Technology	CMOS
Die	128 mm²
Word Size	32 bit
Cores	1
Threads	1
Max Memory	4 GiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Electrical
Vcore	1.75 V
TDP	66 W
TDP (Typical)	58.9 W
Tjunction	0 °C – 95 °C
Tcase	0 °C – 95 °C
Tstorage	-40 °C – 100 °C
Packaging
Package OPGA-453 (PGA) Dimension 49.53 mm x 49.53 mm x 1.942 mm Pitch 1.27 mm Pins 453 Interconnect Socket A (PGA-462)

The Athlon MP 2100+ (OPN AMP2100DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in mid-2002 for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 128 KiB 131,072 B 0.125 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 2-way set associative   L1D$ 64 KiB 65,536 B 0.0625 MiB 1x64 KiB 2-way set associative   L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 16-way set associative

Graphics

This MPU has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

	Supported x86 Extensions & Processor Features
	MMX MMX Extension EMMX Extended MMX Extension 3DNow! 3DNow! Extension E3DNow! Extended 3DNow! Extension SSE Streaming SIMD Extensions x86-16 16-bit x86 x86-32 32-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU SmartMP SmartMP Technology

• Advanced Configuration and Power Interface
  • Halt State
  • Stop Grant State

Documents

Datasheets

• AMD Athlon MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms; Publication # 25480 Rev: D; Issue Date: June 2002.

Others

• System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.